1. Field of the Invention
The present invention relates to the field of computer systems, in particular, the buffering of data in a high speed multi-computer network.
2. Prior Art
In a high speed multi-computer network, data often is transmitted at a much higher rate than it can be consumed. To facilitate high transfer rates between computing nodes, high speed buffers are used. A high speed buffer is typically a First In First Out (FIFO) device through which data that is inserted first, is output first. The functional operating characteristics of FIFO devices is well known. Generally, a FIFO is comprised of a memory device, e.g. a Static Random Access Memory (SRAM), and FIFO controller. The memory device is the media into which data is written and read. A FIFO controller manages the writing and reading of data into the FIFO and provides status and control signals to devices coupled to the FIFO.
When used in a high speed network, a gating factor is the decoding of FIFO pointers for identifying locations in the FIFO where elements are read from or written to. A technique for avoiding the decoding of FIFO pointers is described in an article entitled "Design and Implementation of High-Speed Asynchronous Communication Ports for VLSI Multicomputer Nodes", Yuval Tamir and Jae C. Cho, published in the Proceedings of the 1988 International Symposium on Circuits and Systems Espoo, Finland, June 1988 (TAMIR). TAMIR describes using shift registers to select successive bytes during packet reception and transmission.
Another aspect of FIFO control that affects performance is the generation of control and flag signals. In known systems, the FIFO pointers must be decoded in order to derive the signals. Two FIFO control signals typically provided are EMPTY and FULL. The EMPTY signal is used to indicate that the FIFO has no entries. When an EMPTY signal is asserted, a device connected to the FIFO will know that there is nothing to read from the FIFO. The FULL signal is used to indicate that the FIFO cannot accept further entries. When a FULL signal is asserted, a device connected to the FIFO will know not to attempt to write to the FIFO. Attempts to read from an empty FIFO or write to a full FIFO often result in error conditions.
For a FIFO device operating in a high speed environment, two other signals are typically provided--ALMOST EMPTY and ALMOST FULL. As data transfers in such high speed environments is often in a "burst mode", there may not be time for a device to respond to an EMPTY or FULL signal. Thus, the ALMOST EMPTY and ALMOST FULL signals provide advanced warning to connected device of potential error conditions.
Known techniques for generating control signals require the decoding of FIFO pointers. The FIFO pointers are used to indicate locations in the FIFO, such as top and bottom of the FIFO. The top of the FIFO would identify the next item to be read. The bottom of the FIFO would indicate the location in the FIFO into which data will next be written. The decoding of such FIFO pointers is time consuming and potentially detrimental to the performance of the network.
Further, known techniques for generating flag signals for an asynchronous FIFO are not glitch free. A glitch is a term of art that refers to a signal that under certain conditions, is too short to be detected or does not reach a true logical value. For example, a glitch may occur on an ALMOST EMPTY signal of a FIFO when it is almost empty, and a write operation is immediately followed by a read operation. Under such circumstances, the ALMOST EMPTY signal may not reach a state indicating that the FIFO that is not ALMOST EMPTY. This may provide improper state information to devices utilizing the FIFO signals.
It would be desirable to generate FIFO control signals without decoding FIFO pointers and to eliminate instances where a signal glitch may occur.